Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Algorithms for automatic transistor sizing in CMOS digital circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
ARIES: A workstation based, schematic driven system for circuit design
DAC '84 Proceedings of the 21st Design Automation Conference
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
P.SIZE: a sizing aid for optimized designs
EURO-DAC '92 Proceedings of the conference on European design automation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An iterative gate sizing approach with accurate delay evaluation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Migration: a new technique to improve synthesized designs through incremental customization
DAC '98 Proceedings of the 35th annual Design Automation Conference
A power optimization method considering glitch reduction by gate sizing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gate sizing with controlled displacement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Power-delay optimizations in gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Macro-driven circuit design methodology for high-performance datapaths
Proceedings of the 37th Annual Design Automation Conference
Optimal P/N width ratio selection for standard cell libraries
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Post-layout transistor sizing for power reduction in cell-based design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Technology-based transformations
Logic Synthesis and Verification
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Simultaneous gate sizing and fanout optimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Layout-driven Timing Optimization by Generalized De Morgan Transform
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Proceedings of the 42nd annual Design Automation Conference
Application of fast SOCP based statistical sizing in the microprocessor design flow
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A novel approach for variation aware power minimization during gate sizing
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Mapping for better than worst-case delays in LUT-based FPGA designs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A linear programming formulation for security-aware gate sizing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
An expected-utility based approach to variation aware VLSI optimization under scarce information
Proceedings of the 13th international symposium on Low power electronics and design
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
Proceedings of the 13th international symposium on Low power electronics and design
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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In this paper a solution is presented to tune the delay of a circuit composed of cells to a prescribed value, while minimizing power consumption. The tuning is performed by adapting the load drive capabilities of the cells. This optimization problem is mapped onto a linear program, which is then solved by the Simplex algorithm. This approach guarantees to find the global optimum, and has proven feasible for circuits of up to several thousand cells. The method can be used with any convex delay model. Results show that circuits can be speeded up by a factor of 2 at a cost of only 10 to 30% of extra power.