Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Linear programming for sizing, Vth and Vdd assignment
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Handbook of Approximation Algorithms and Metaheuristics (Chapman & Hall/Crc Computer & Information Science Series)
"Go with the winners" algorithms
SFCS '94 Proceedings of the 35th Annual Symposium on Foundations of Computer Science
Revisiting the linear programming framework for leakage power vs. performance optimization
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing for large cell-based designs
Proceedings of the Conference on Design, Automation and Test in Europe
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-length biasing for runtime-leakage control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Numerically Convex Forms and Their Application in Gate Sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Strongly NP-hard discrete gate-sizing problems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new adaptive multi-start technique for combinatorial global optimizations
Operations Research Letters
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
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The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including Vt and Lg. Within the research-oriented infrastructure used in the ISPD 2012 Gate Sizing Contest, we develop a metaheuristic approach to gate sizing that integrates timing and power optimization, and handles several types of constraints. Our solutions are evaluated using a rigorous protocol that computes circuit delay with Synopsys PrimeTime. Our implementation Trident outperforms the best-reported results on all but one of the ISPD 2012 benchmarks. Compared to the 2012 contest winner, we further reduce leakage power by an average of 43%.