Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
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The discrete gate-sizing problem has been studied by several researchers recently. Some complexity results have been obtained, and a number of heuristic algorithms have been proposed. For circuit networks that are restricted to the set of trees, or series-parallel graphs, pseudo-polynomial time algorithms to obtain the exact solution have also been proposed, though none can be extended to circuit networks that are arbitrary directed acyclic graphs (dags), We prove that the problem is strongly NP-hard. Our result implies that for arbitrary dags, there is no pseudo-polynomial time algorithm to obtain the exact solution unless P=NP. We also prove that the absolute approximation discrete gate sizing problem is strongly NP-hard. These results provide insight into the difficulties of the problem and may lead to better heuristics