Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Combinatorial cell design for CMOS libraries
Integration, the VLSI Journal - Special issue on timing closure
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Leakage in nano-scale technologies: mechanisms, impact and design considerations
Proceedings of the 41st annual Design Automation Conference
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Standard cell library optimization for leakage reduction
Proceedings of the 43rd annual Design Automation Conference
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recovery-driven design: a power minimization methodology for error-tolerant processor modules
Proceedings of the 47th Design Automation Conference
Slack redistribution for graceful degradation under voltage overscaling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
Post-synthesis leakage power minimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power without sacrificing performance. In this paper, we present an effective and scalable transistor-level Vth assignment approach and show leakage reduction over standard cell-level Vth assignment. The main disadvantage of transistor-level Vth assignment is increased cell library size and characterization effort. In comparison to previous approaches, our approach yields better solution quality, requires smaller cell library, is more accurate in considering the impact of Vth assignment on propagation delay, slew (transition delay) and capacitance, and is significantly faster.