Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
EVAL: Utilizing processors with variation-induced timing errors
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Revisiting the linear programming framework for leakage power vs. performance optimization
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Gate-length biasing for runtime-leakage control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overscaling-friendly timing speculation architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Recovery-driven design: a power minimization methodology for error-tolerant processor modules
Proceedings of the 47th Design Automation Conference
Scalable stochastic processors
Proceedings of the Conference on Design, Automation and Test in Europe
Architecting processors to allow voltage/reliability tradeoffs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Stochastic computing: embracing errors in architectureand design of processors and applications
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
A self-evolving design methodology for power efficient multi-core systems
Proceedings of the International Conference on Computer-Aided Design
Analysis of circuit dynamic behavior with timed ternary decision diagram
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 9th conference on Computing Frontiers
A methodology for energy-quality tradeoff using imprecise hardware
Proceedings of the 49th Annual Design Automation Conference
SALSA: systematic logic synthesis of approximate circuits
Proceedings of the 49th Annual Design Automation Conference
On software design for stochastic processors
Proceedings of the 49th Annual Design Automation Conference
Compiling for energy efficiency on timing speculative processors
Proceedings of the 49th Annual Design Automation Conference
CCP: common case promotion for improved timing error resilience with energy efficiency
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A self-tuning design methodology for power-efficient multi-core systems
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
Exploiting Timing Error Resilience in Processor Architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Proceedings of the Conference on Design, Automation and Test in Europe
On testing timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
Relax-and-retime: a methodology for energy-efficient recovery based design
Proceedings of the 50th Annual Design Automation Conference
Post-placement voltage island generation for timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
ForTER: a forward error correction scheme for timing error resilience
Proceedings of the International Conference on Computer-Aided Design
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Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. We propose a designlevel approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. We increase the range of voltage values at which the (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner. The resulting designs heuristically minimize the voltage at which the maximum allowable error rate is encountered, thus minimizing power consumption for a prescribed maximum error rate and allowing the design to fail more gracefully. Compared with baseline designs, we achieve a maximum of 32.8% and an average of 12.5% power reduction at an error rate of 2%. The area overhead of our techniques, as evaluated through physical implementation (synthesis, placement and routing), is no more than 2.7%.