Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
Slack redistribution for graceful degradation under voltage overscaling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Minimum-Energy Operation Via Error Resiliency
IEEE Embedded Systems Letters
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Relax-and-retime: a methodology for energy-efficient recovery based design
Proceedings of the 50th Annual Design Automation Conference
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Better-Than-Worst-case (BTW) design has been proposed as an alternative way to operate a circuit by deliberately allowing timing errors for rare cases and rectifying them with error correction mechanisms in order to achieve higher performance, better reliability guarantee, or lower energy consumption. This new design methodology necessitates the analysis and manipulation of signal probabilities during circuit optimization. This paper looks for the solution from the logic synthesis perspective and proposes a new concept, called Common Case Promotion (CCP), to enable effective circuit optimization following the BTW design methodology. CCP consists of: 1) probability-driven re-synthesis that changes a digital circuit's internal structure, 2) a dynamic behavior aware SAT-based redundancy remover that reduces area overhead, and 3) a timed characteristic function (TCF) based circuit dynamic behavior analyzer that provides optimization convergence. The experimental results show that, on average, we can effectively improve circuits' timing error resilience by 24%, which reduces the need of error recovery for BTW circuits considerably, and we can improve the overall energy efficiency by 15%.