Relax-and-retime: a methodology for energy-efficient recovery based design

• Authors: Shankar Ganesh Ramasubramanian;Swagath Venkataramani;Adithya Parandhaman;Anand Raghunathan
• Venue: Proceedings of the 50th Annual Design Automation Conference
• Year: 2013

Recovery based design (RBD) is a promising approach for the design of energy-efficient circuits under variations. RBD instruments circuits with mechanisms to identify and correct timing violations, thereby allowing reduced guard bands or design margins. In addition, RBD enables aggressive voltage overscaling to a point where timing errors occur even under nominal conditions. A major barrier to the widespread adoption of RBD is that traditional design practices and synthesis tools result in circuits with so-called"path walls", leading to an explosion in the number of timing errors beyond a certain critical operating voltage. To alleviate this effect, previous techniques focused on combinational circuit optimizations such as sizing, use of dual Vth cells, re-structuring, etc. to favorably reshape the path delay distribution. However, these techniques are limited by the inherent sequential structure of the circuit, which defines the boundaries of the combinational logic. In this work, we explore a completely different approach to synthesize circuits for RBD. We propose the use of retiming, a well-known and powerful sequential optimization technique to redefine the boundaries of combinational logic, thereby creating new opportunities for RBD that cannot be explored by previous techniques. We make the key observation that, in retiming circuits with RBD (unlike classical retiming), it is acceptable for a few paths in the circuit to exceed the clock period. Using this insight, we propose a synthesis methodology, Relax-and-Retime, wherein the original circuit is relaxed by ignoring timing constraints on selected paths that are bottlenecks to retiming. When classical minimum period retiming is employed on this relaxed circuit, the path wall is shifted to a lower delay, thus allowing additional voltage overscaling. The Relax-and-Retime methodology judiciously selects bottleneck paths by trading off recovery overheads caused by timing errors due to these paths with the opportunities for retiming. We utilize the proposed methodology to synthesize a wide range of benchmarks including arithmetic circuits, ISCAS89 benchmarks and modules from the UltraSPARC T1 processor. Our results demonstrate 9-25% (average of 15.3%) improvement in overall energy compared to a well-optimized baseline with RBD.