Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Proceedings of the 42nd annual Design Automation Conference
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
Proceedings of the conference on Design, automation and test in Europe
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trifecta: a nonspeculative scheme to exploit common, data-dependent subcritical paths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CCP: common case promotion for improved timing error resilience with energy efficiency
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-Vth etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set of possible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated.