Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Speed binning aware design methodology to improve profit under parameter variations
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
Proceedings of the conference on Design, automation and test in Europe
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Process-variation resilient and voltage scalable DCT architecture for robust low-power computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling and resource binding algorithm considering timing variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods
Proceedings of the International Conference on Computer-Aided Design
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Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for statistical timing analysis using Levelized Covariance Propagation (LCP). The algorithm simultaneously considers the impact of random placement of dopants (which makes every transistor in a die independent in terms of threshold voltage) and the spatial correlation of the process parameters such as channel length, transistor width and oxide thickness due to the intra-die variations. It also considers the signal correlation due to reconvergent paths in the circuit. Results on several benchmark circuits in 70nm technology show an average of 0.21% and 1.07% errors in mean and the standard deviation, respectively, in timing analysis using the proposed technique compared to the Monte-Carlo analysis.