Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
A new framework for static timing analysis, incremental timing refinement, and timing simulation
ATS '00 Proceedings of the 9th Asian Test Symposium
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Block remap with turnoff: a variation-tolerant cache design technique
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Process variation aware issue queue design
Proceedings of the conference on Design, automation and test in Europe
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Instruction scheduling for VLIW processors under variation scenario
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
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Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware yield model, based on which we present a statistical design methodology to improve profit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve the profitability of design over an initial yield-optimized design. We also propose an algorithm to determine optimal bin boundaries for maximizing profit with frequency binning. Finally, we present an integrated design methodology for simultaneous sizing and bin placement to enhance profit under an area constraint. Experiments on a set of ISCAS85 benchmarks show up to 26% (36%) improvement in profit for fixed bin (for simultaneous sizing and bin placement) with three frequency bins considering both leakage and delay bounds compared to a design optimized for 90% yield at iso-area.