Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Convex Optimization
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Speed binning aware design methodology to improve profit under parameter variations
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Binning optimization based on SSTA for transparently-latched circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
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High performance applications are highly affected by process variations due to considerable spread in their expected frequencies after fabrication. Typically "binning" is applied to those chips that are not meeting their performance requirement after fabrication. Using binning, such failing chips are sold at a loss (e.g., proportional to the degree that they are failing their performance requirement). This paper discusses a gate-sizing algorithm to minimize "yield-loss" associated with binning. We propose a binning yield-loss function as a suitable objective to be minimized. We show this objective is convex with respect to the size variables and consequently can be optimally and efficiently solved. These contributions are yet made without making any specific assumptions about the sources of variability or how they are modeled. We show computation of the binning yield-loss can be done via any desired statistical static timing analysis (SSTA) tool. The proposed technique is compared with a recently proposed sensitivity-based statistical sizer, a deterministic sizer with worst-case variability estimate, and a deterministic sizer with relaxed area constraint. We show consistent improvement compared to the sensitivity-based approach in quality of solution (final binning yield-loss value) as well as huge run-time gain. Moreover, we show that a deterministic sizer with a relaxed area constraint will also result in reasonably good binning yield-loss values for the extra area overhead.