Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

Authors:
B. Rebaud;M. Belleville;E. Beigné;C. Bernard;M. Robert;P. Maurine;N. Azemard
Affiliations:
CEA, LETI, MINATEC campus, F38054 Grenoble Cedex, France;CEA, LETI, MINATEC campus, F38054 Grenoble Cedex, France;CEA, LETI, MINATEC campus, F38054 Grenoble Cedex, France;CEA, LETI, MINATEC campus, F38054 Grenoble Cedex, France;LIRMM, Montpellier, France;LIRMM, Montpellier, France;LIRMM, Montpellier, France
Venue:
Microelectronics Journal
Year:
2011

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Abstract

To compensate the variability effects in advanced technologies, Process, Voltage, Temperature (PVT) monitors are mandatory to use Adaptive Voltage Scaling (AVS) or Adaptive Body Biasing (ABB) techniques. This paper describes a new monitoring system, allowing failure anticipation in real-time, looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of dedicated sensor structures located near monitored flip-flop, coupled with a specific timing detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45nm low power technology, demonstrate a scalable, low power and low area system, and its compatibility with a standard CAD flow. Gains between an AVFS scheme based on those structures and a standard DVFS are given for a 32bits VLIW DSP.