Modified Stability Checking for On-line Error Detection

Authors:
Satish Yada;Bharadwaj Amrutur;Rubin A. Parekhji
Affiliations:
Indian Institute of Science, Bangalore, India.;Indian Institute of Science, Bangalore, India.;Texas Instruments (India) Pvt. Ltd., Bangalore, India.
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

Citing 0
Cited 2

False Error Vulnerability Study of On-line Soft Error Detection Mechanisms

Journal of Electronic Testing: Theory and Applications
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a unified error detection technique, based on stability checking, for on-line detection of delay, crosstalk and transient faults in combinational circuits and SEUs in sequential elements. Our method, called Modified Stability Checking (MSC), overcomes the limitations of the earlier stability checking methods. We also propose a novel checker circuit to realize this scheme. The checker is self-checking for a wide set of realistic internal faults including transient faults. Extensive circuit simulations have been done to characterize the checker circuit. A prototype checker circuit for a 1mm2 standard cell array has been implemented in a 0.13um process.