Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Linear programming for sizing, Vth and Vdd assignment
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
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Foundations and Trends in Electronic Design Automation
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Robust interconnect communication capacity algorithm by geometric programming
Proceedings of the 2009 international symposium on Physical design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaRS: parallel and near-optimal grid-based cell sizing for library-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. Since the delay under this model is a convex function, optimal sizing algorithms based on convex programming techniques are applied with the new delay model. Experimental results demonstrating the accuracy of proposed model are presented along with results of sizing various test circuits