Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Similarity Search in High Dimensions via Hashing
VLDB '99 Proceedings of the 25th International Conference on Very Large Data Bases
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaRS: parallel and near-optimal grid-based cell sizing for library-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Gate sizing for large cell-based designs
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On incremental component implementation selection in system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Shedding physical synthesis area bloat
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Proceedings of the International Conference on Computer-Aided Design
Simultaneous clock and data gate sizing algorithm with common global objective
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Fast and efficient lagrangian relaxation-based discrete gate sizing
Proceedings of the Conference on Design, Automation and Test in Europe
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shift, the problem of discrete gate sizing has received significantly less attention than its continuous counterpart. On the other hand, cell sizes of many realistic libraries are sparse, for example, geometrically spaced, which makes the nearest rounding approach inapplicable as large timing violations may be introduced. Therefore, it is highly desirable to design an effective algorithm to handle this discrete gate sizing problem. Such an algorithm is proposed in this paper. The algorithm is a continuous solution guided dynamic programming approach. A set of novel techniques, such as Locality Sensitive Hashing based solution selection and stage pruning, are also proposed to accelerate the algorithm and improve the solution quality. Our experimental results demonstrate that (1) nearest rounding approach often leads to large timing violations and (2) compared to the well-known Coudert's approach, the new algorithm saves 9% -- 31% in area cost while still satisfying the timing constraint.