First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Binary Quadratic Forms: An Algorithmic Approach (Algorithms and Computation in Mathematics)
Binary Quadratic Forms: An Algorithmic Approach (Algorithms and Computation in Mathematics)
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A general framework for spatial correlation modeling in VLSI design
Proceedings of the 44th annual Design Automation Conference
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Principle Hessian direction based parameter reduction with process variation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Modeling the Driver Load in the Presence of Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. To accurately consider both global and local process variations, a large number of random variables (or parameters) have to be incorporated into circuit models. This in turn raises the complexity of the circuit models. In this paper, we propose a principle Hessian direction-based parameter-reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In interconnect cases, the proposed method reduces 70% of parameters. In some cases, for example, the mesh circuit in the current paper, the new approach leads to an 85% reduction. We also tested ISCAS benchmarks. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.