First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Binary Quadratic Forms: An Algorithmic Approach (Algorithms and Computation in Mathematics)
Binary Quadratic Forms: An Algorithmic Approach (Algorithms and Computation in Mathematics)
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Modeling the Driver Load in the Presence of Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 45th annual Design Automation Conference
Adjustment-based modeling for statistical static timing analysis with high dimension of variability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 46th Annual Design Automation Conference
Efficient design-specific worst-case corner extraction for integrated circuits
Proceedings of the 46th Annual Design Automation Conference
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Proceedings of the 46th Annual Design Automation Conference
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
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As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessian Direction (PHD) based parameter reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis (PCA) method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.