Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Authors:
Fa Wang;Wangyang Zhang;Shupeng Sun;Xin Li;Chenjie Gu
Affiliations:
Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Strategic CAD Labs, Intel Corporation, Hillsboro, OR
Venue:
Proceedings of the 50th Annual Design Automation Conference
Year:
2013

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Abstract

Efficient high-dimensional performance modeling of today's complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient high-dimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9x runtime speedup over the traditional modeling technique without surrendering any accuracy.