A methodology for concurrent fabrication process/cell library optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Design of robust test criteria in analog testing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling
Analog Integrated Circuits and Signal Processing - Analog circuit techniques and related topics
Proceedings of the 38th annual Design Automation Conference
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Defining Cost Functions for Robust IC Design and Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Proceedings of the 42nd annual Design Automation Conference
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Robust analog/RF circuit design with projection-based posynomial modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Projection-based performance modeling for inter/intra-die variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 45th annual Design Automation Conference
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Efficient design-specific worst-case corner extraction for integrated circuits
Proceedings of the 46th Annual Design Automation Conference
Yield-driven iterative robust circuit optimization algorithm
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we present a new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization. Circuit performance measures are modeled as response surfaces of the designable and uncontrollable (noise) parameters. Worst-case analysis proceeds by first computing the worst-case circuit performance value and then determining the worst-case noise parameter values by solving a nonlinear programming problem. A new circuit optimization technique is developed to find an optimal design point at which all of the circuit specifications are met under worst-case conditions. This worst-case design optimization method is formulated as a constrained multicriteria optimization. The methodologies described in this paper are applied to several VLSI circuits to demonstrate their accuracy and efficiency