A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling

Authors:
Seiji Funaba;Akihiro Kitagawa;Toshiro Tsukada;Goichi Yokomizo
Affiliations:
Semiconductor and Integrated Circuits Group, Hitachi, Ltd., Kokubunji-shi, 185–8601 Japan;Semiconductor and Integrated Circuits Group, Hitachi, Ltd., Kokubunji-shi, 185–8601 Japan;Semiconductor and Integrated Circuits Group, Hitachi, Ltd., Kokubunji-shi, 185–8601 Japan;Semiconductor and Integrated Circuits Group, Hitachi, Ltd., Kokubunji-shi, 185–8601 Japan
Venue:
Analog Integrated Circuits and Signal Processing - Analog circuit techniques and related topics
Year:
2000

Citing 3
Cited 1

Practical methods of optimization; (2nd ed.)

Practical methods of optimization; (2nd ed.)
An intelligent design system for analogue integrated circuits

EURO-DAC '90 Proceedings of the conference on European design automation
Worst-case analysis and optimization of VLSI circuit performances

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Chameleon ART: a non-optimization based analog design migration framework

Proceedings of the 43rd annual Design Automation Conference

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Abstract

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 h, making this method 5 times more efficient than conventional methods.