Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Authors:
Xin Li;Wangyang Zhang;Fa Wang;Shupeng Sun;Chenjie Gu
Affiliations:
Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Intel Strategic CAD Labs, Hillsboro, OR
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2012

Citing 13
Cited 3

Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient analog circuit synthesis with simultaneous yield and robustness optimization

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Discrete-time signal processing (2nd ed.)

Discrete-time signal processing (2nd ed.)
Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search

Proceedings of the 38th annual Design Automation Conference
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments

Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
Convex Optimization

Convex Optimization
Digital Image Processing (3rd Edition)

Digital Image Processing (3rd Edition)
Statistical Performance Modeling and Optimization

Statistical Performance Modeling and Optimization
Stochastic analog circuit behavior modeling by point estimation method

Proceedings of the 2011 international symposium on Physical design
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic Probability Extraction for Nonnormal Performance Distributions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quadratic Statistical Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case analysis and optimization of VLSI circuit performances

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Proceedings of the 50th Annual Design Automation Conference
Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Proceedings of the 50th Annual Design Automation Conference
Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75X runtime speedup over the traditional kernel estimation method.