Simulation and the Monte Carlo Method
Simulation and the Monte Carlo Method
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
A statistical performance simulation methodology for VLSI circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
A method for linking process-level variability to system performances
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Structural Fault Based Specification Reduction for Testing Analog Circuits
Journal of Electronic Testing: Theory and Applications
7.4 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 44th annual Design Automation Conference
Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A scalable σ-space based methodology for modeling process parameter variations in analog circuits
Microelectronics Journal
Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Behavior-level yield enhancement approach for large-scaled analog circuits
Proceedings of the 47th Design Automation Conference
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion
Proceedings of the International Conference on Computer-Aided Design
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A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.