Behavioral modeling phase-locked loops for mixed-mode simulation
Analog Integrated Circuits and Signal Processing - Special issue: modeling and simulation of mixed analog-digital systems
Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Automatic Behavioural Model Calibration for Efficient PLL System Verification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
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In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL circuits more quickly by using Verilog-AMS language. Not only top-down applications but also bottom-up applications can be supported by using our PLL models. The main idea is to use a special "characterization mode" to get critical circuit parameters. In the characterization mode, only two input patterns are enough to get circuit properties with parasitic effects. In the experimental results, we will build an accurate PLL behavioral models for demonstration compared to the HSPICE results and typical behavioral models.