Automatic Behavioural Model Calibration for Efficient PLL System Verification

Authors:
Ayman Mounir;Ahmed Mostafa;Maged Fikry
Affiliations:
Mentor Graphics Egypt;Mentor Graphics Egypt;Mentor Graphics Egypt
Venue:
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Year:
2003

Citing 2
Cited 3

Behavioral modeling phase-locked loops for mixed-mode simulation

Analog Integrated Circuits and Signal Processing - Special issue: modeling and simulation of mixed analog-digital systems
Practical synthesis of high-performance analog circuits

Practical synthesis of high-performance analog circuits

An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast statistical analysis of process variation effects using accurate PLL behavioral models

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Behavioural models selected from a predefined library are automatically calibrated against transistor-level blocks from a gigahertz-range PLL undergoing verification. The calibrated behavioural models simulate at 10 to 200 times the speed of the target blocks with insignificant loss of accuracy. The technique shrinks the overall simulation time of the assembled PLL by a factor of 120. We rely on a set of carefully qualified, detailed behavioural models, written in VHDL-AMS, each with a custom calibration plan.