7.4 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits

Authors:
H. Yoon;P. Variyam;A. Chatterjee;N. Nagi
Affiliations:
-;-;-;-
Venue:
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Year:
1998

Citing 4
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Abstract

In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.