Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A method for linking process-level variability to system performances
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Projection-based performance modeling for inter/intra-die variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AMGIE-A synthesis environment for CMOS analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WATSON: design space boundary exploration and model generation for analog and RFIC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quadratic Statistical Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this work tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed nominal point moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each sub-block, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on a complex CPPLL design, this behavior-level approach could be another efficient methodology to help designers improve their analog circuits toward better yield.