DARWIN: CMOS opamp synthesis by means of a genetic algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Feasibility and performance region modeling of analog and digital circuits
Analog Integrated Circuits and Signal Processing - Special issue: modeling and simulation of mixed analog-digital systems
Numerical Recipes in C++: the art of scientific computing
Numerical Recipes in C++: the art of scientific computing
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Multiobjective evolutionary algorithms: classifications, analyses, and new innovations
Multiobjective evolutionary algorithms: classifications, analyses, and new innovations
Scalable trajectory methods for on-demand analog macromodel extraction
Proceedings of the 42nd annual Design Automation Conference
Comparison of Multiobjective Evolutionary Algorithms: Empirical Results
Evolutionary Computation
Design and Modeling for Computer Experiments (Computer Science & Data Analysis)
Design and Modeling for Computer Experiments (Computer Science & Data Analysis)
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Synthesis of high-performance analog circuits in ASTRX/OBLX
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design automation for analog: the next generation of tool challenges
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simulation-based reusable posynomial models for MOS transistor parameters
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
COSMO: a correlation sensitive mutation operator for multi-objective optimization
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Yield-aware hierarchical optimization of large analog integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior-level yield enhancement approach for large-scaled analog circuits
Proceedings of the 47th Design Automation Conference
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances
Proceedings of the 47th Design Automation Conference
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Supervised design space exploration by compositional approximation of Pareto sets
Proceedings of the 48th Design Automation Conference
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Variability aware SVM macromodel based design centering of analog circuits
Analog Integrated Circuits and Signal Processing
Efficient design space exploration for component-based system design
Proceedings of the International Conference on Computer-Aided Design
ITRS 2011 analog EDA challenges and approaches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.