The nature of statistical learning theory
The nature of statistical learning theory
Least Squares Support Vector Machine Classifiers
Neural Processing Letters
Proceedings of the 38th annual Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A combined feasibility and performance macromodel for analog circuits
Proceedings of the 42nd annual Design Automation Conference
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Proceedings of the 43rd annual Design Automation Conference
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the 44th annual Design Automation Conference
Analog Design Centering and Sizing
Analog Design Centering and Sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog Integrated Circuits and Signal Processing
Efficient handling of operating range and manufacturing line variations in analog cell synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90 nm UMC technology (Euro-practice).