Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines

Authors:
Tholom Kiely;Georges Gielen
Affiliations:
-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Year:
2004

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Abstract

This paper describes the application of Least-Squares Support Vector Machine (LS-SVM) training to analog circuit performance modeling as needed for accelerated or hierarchical analog circuit synthesis. The training is a type of regression, where a function of a special form is fit to experimental performance data derived from analog circuit simulations. The method is contrasted with a feasibility model approach based on the more traditional use of SVMs, namely classification. A Design of Experiments (DOE) strategy is reviewed which forms the basis of an efficient simulation sampling scheme. The results of our functional regression are then compared to two other DOE-based fitting schemes: a simple linear least-squares regression and a regression using posynomial models. The LS-SVM fitting has advantages over these approaches in terms of accuracy of fit to measured data, prediction of intermediatedata points and reduction of free model tuning parameters.