Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Proceedings of the 43rd annual Design Automation Conference
Design and Modeling for Computer Experiments (Computer Science & Data Analysis)
Design and Modeling for Computer Experiments (Computer Science & Data Analysis)
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design
KES '09 Proceedings of the 13th International Conference on Knowledge-Based and Intelligent Information and Engineering Systems: Part II
Design of parasitic and process-variation aware nano-CMOS RF circuits: a VCO case study
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A graph grammar based approach to automated multi-objective analog circuit design
Proceedings of the Conference on Design, Automation and Test in Europe
CMOS Circuit Design, Layout, and Simulation
CMOS Circuit Design, Layout, and Simulation
Design illustration of a symmetric OTA using multiobjective genetic algorithms
KES'11 Proceedings of the 15th international conference on Knowledge-based and intelligent information and engineering systems - Volume Part III
PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression
ISED '11 Proceedings of the 2011 International Symposium on Electronic System Design
Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
A Multiobjective Optimization-Based Evolutionary Algorithm for Constrained Optimization
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
WATSON: design space boundary exploration and model generation for analog and RFIC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications
ISVLSI '12 Proceedings of the 2012 IEEE Computer Society Annual Symposium on VLSI
| Hi-index | 0.00 |
Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance yield. Mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have largely automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills and design cycle time. In this paper, two novel design flows are presented for fast multiobjective optimization of nano-CMOS circuits: actual-value optimization and normalized-value optimization. The design flows consider two characteristics for optimization i.e. power and frequency in a current-starved 50nm voltage-controlled oscillator (VCO). Accurate polynomial-regression based models have been developed for power (including leakage) and frequency of the VCO to speedup the design optimization. In the actual-value optimization flow, the power model is minimized using genetic algorithm, while treating frequency =100MHz as a constraint. The actual-value optimization flow achieved 21.67% power savings, while maintaining a frequency =100MHz. In the normalized-value optimization flow, the normalized form of these models are subjected to a weighted optimization using genetic algorithm. The normalized-value optimization flow achieved 16.67% power savings, with frequency =100MHz. It is observed that while the actual-value optimization approach provides a better exploration of the design space, the normalized-value optimization approach provides a ~5x speedup in the computation time.