Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Support vector machines for analog circuit performance representation
Proceedings of the 40th annual Design Automation Conference
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Robust analog/RF circuit design with projection-based posynomial modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Proceedings of the 43rd annual Design Automation Conference
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Yield-aware hierarchical optimization of large analog integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior-level yield enhancement approach for large-scaled analog circuits
Proceedings of the 47th Design Automation Conference
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances
Proceedings of the 47th Design Automation Conference
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Robust spatial correlation extraction with limited sample via L1-norm penalty
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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Automated circuit optimization is an important component of complex analog integrated circuit design. Today's analog designs must be optimized not only for nominal performance but also for robustness in order to maintain a reasonable yield with highly scaled VLSI technologies. The complex nature of analog/mixed-signal systems, however, makes this yield-aware analog circuit optimization extremely difficult and costly. In this paper, we adopt a Geostatistics motivated approach (i.e. Kriging model) for efficient extraction of yield-aware Pareto front performance models for analog circuits. An iterative search based optimization approach is proposed to efficiently seek optimal performance tradeoffs under yield constraints in high-dimensional design parameter and process variation spaces. Our experiments confirm that the generated yield-aware Pareto fronts are accurate and the optimization procedure is very efficient. The latter is achieved by the well controlled iterative update scheme in the presented techniques which avoids an excessive number of time consuming transistor-level simulations.