Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Computer-Aided Design of Analog Integrated Circuits and Systems
Computer-Aided Design of Analog Integrated Circuits and Systems
A Model of Computation for Continuous-Time "-" Modulators
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Comparison of Multiobjective Evolutionary Algorithms: Empirical Results
Evolutionary Computation
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
Performance assessment of multiobjective optimizers: an analysis and review
IEEE Transactions on Evolutionary Computation
A high-level simulation and synthesis environment for ΔΣ modulators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers
Proceedings of the 43rd annual Design Automation Conference
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
COSMO: a correlation sensitive mutation operator for multi-objective optimization
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design
Microelectronics Journal
Analog Integrated Circuits and Signal Processing
Contract-based system-level composition of analog circuits
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Behavior-level yield enhancement approach for large-scaled analog circuits
Proceedings of the 47th Design Automation Conference
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Supervised design space exploration by compositional approximation of Pareto sets
Proceedings of the 48th Design Automation Conference
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
Analog Integrated Circuits and Signal Processing
Efficient design space exploration for component-based system design
Proceedings of the International Conference on Computer-Aided Design
Operating-point driven formulation for analog computer-aided design
Analog Integrated Circuits and Signal Processing
Modeling and design of CMOS analog circuits through hierarchical abstraction
Integration, the VLSI Journal
Synthesis of planar inductors in low temperature co-fired ceramic technology
Analog Integrated Circuits and Signal Processing
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An efficient methodology is presented to generate the Pareto-optimal hypersurface of the performance space of a complete mixed-signal electronic system. This Pareto-optimal front offers the designeraccess to all optimal design solutions: starting from the performance specifications, a satisfactory point can a posteriori be selected on the hypersurface which immediately determines the final design parameters. Fast execution is guaranteed by using multi-objective evolutionary optimization techniques and hierachical decomposition. The presented method takes advantage of the Pareto hypersurfaces of the subblocks to generate the overall Pareto front. The hierarchical approach combines behavioral simulation with behavioral models at the higher levels, with SPICE simulations with transistor-level accuracy at the lowest level. Storing the performance data of all subblocks enables reuse for other systems later on.