Optimal design of delta-sigma ADCs by design space exploration
Proceedings of the 39th annual Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Wireless OFDM Systems: How to Make Them Work?
Wireless OFDM Systems: How to Make Them Work?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
A high-level simulation and synthesis environment for ΔΣ modulators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
Analog Integrated Circuits and Signal Processing
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This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.