Proceedings of the conference on Design, automation and test in Europe
CAD solutions and outstanding challenges for mixed-signal and RFIC design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Hierarchical extraction and verification of symmetry constraints for analog layout automation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Multi-level approach for integrated spiral inductor optimization
Proceedings of the 42nd annual Design Automation Conference
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Robust automated synthesis methodology for integrated spiral inductors with variability
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing
Design optimization of switchable multi-port spiral inductors
Analog Integrated Circuits and Signal Processing
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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In this paper we present SOC-NLNA, a systematic synthesis methodology for fully integrated narrow-band CMOS Low Noise Amplifiers (LNA) in high performance System-on-Chip (SoC) designs. SOC-NLNA is based on deterministic numerical nonlinear optimization and the Normal Boundary Intersection (NBI) method for Pareto optimization. To enable SoC integration, we simultaneously optimize both devices and passive components to yield integrated inductor values that are significantly less than those generated by traditional design techniques. When the synthesized LNAs are simulated using Cadence SpectreRF, SOC-NLNA yields up to 35 and 58 percent improvement in noise figure and gain. Leveraging the efficiency of our methodology, we are able to generate the Pareto surfaces between LNA performance metrics in seconds.