Proceedings of the conference on Design, automation and test in Europe
CAD solutions and outstanding challenges for mixed-signal and RFIC design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Hierarchical extraction and verification of symmetry constraints for analog layout automation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Multi-level approach for integrated spiral inductor optimization
Proceedings of the 42nd annual Design Automation Conference
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Robust automated synthesis methodology for integrated spiral inductors with variability
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Analytical wide-band modeling of high frequency resistance in integrated spiral inductors
Analog Integrated Circuits and Signal Processing
Applied Optimization with MATLAB Programming
Applied Optimization with MATLAB Programming
Analog Integrated Circuits and Signal Processing
WATSON: design space boundary exploration and model generation for analog and RFIC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variability-Aware Multilevel Integrated Spiral Inductor Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a systematic synthesis methodology for fully integrated narrow-band CMOS low-noise amplifiers (LNAs) in high-performance system-on-chip (SoC) designs. The methodology is based on deterministic gradient-based numerical nonlinear optimization and the normal boundary intersection (NBI) method for Pareto optimization. We simultaneously optimize transistor widths, bias voltages, and input and output matching network passive components, which yields integrated inductor values that are more than one order of magnitude less than those generated by several existing equation-based LNA design techniques. By generating significantly smaller inductor values, we enable the SoC integration of the complete LNA. When the synthesized LNAs are characterized using circuit-level simulation, our methodology yields up to 35% and 58% improvement in noise figure and gain, respectively.