General AC constraint transformation for analog ICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hierarchical constraint transformation using directed interval search for analog system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Proceedings of the 42nd annual Design Automation Conference
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Robust system level design with analog platforms
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Reconfigurable ΔΣ modulator topology design through hierarchical mapping and constraint extraction
Integration, the VLSI Journal
Analog circuits optimization based on evolutionary computation techniques
Integration, the VLSI Journal
ASLIC: A low power CMOS analog circuit design automation
Integration, the VLSI Journal
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Fast Exploration Procedure for Analog High-Level Specification Translation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper discusses about analog circuit design methodology through hierarchical abstraction. A method of translating optimal specifications from a higher level of an hierarchy to a lower level, has been proposed. The specification-translation method has been integrated with an existing Geometric Programming based robust CMOS analog circuit sizing method. A 4th order, Sallen-Key low-pass filter has been designed using the integrated top-down design methodology targeting a 0.18@mm technology. Total time taken to design the circuit is approximately 1.5h. A good agreement between simulated performances of the final design with targeted specification proves efficiency of the methodology.