A statistical performance simulation methodology for VLSI circuits

Authors:
Michael Orshansky;James C. Chen;Chenming Hu
Affiliations:
Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA;Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA;Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.