A statistical performance simulation methodology for VLSI circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Estimation for maximum instantaneous current through supply lines for CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Test Consideration for Nanometer-Scale CMOS Circuits
IEEE Design & Test
Efficient variation-aware statistical dynamic timing analysis for delay test applications
Proceedings of the Conference on Design, Automation and Test in Europe
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Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating the test quality with respect to timing defects under process variations. Based on the proposed metric and a dynamic timing analyzer, we develop a pattern-selection algorithm for selecting the minimal number of patterns that can achieve the maximal test quality. To shorten the runtime in dynamic timing analysis, we propose an algorithm to speed up the Monte-Carlo-based simulation. Our experimental results show that, selecting a small percentage of patterns from a multiple-detection transition fault pattern set is suf.cient to maintain the test quality given by the entire pattern set. We present run-time and accuracy comparisons to demonstrate the efficiency and effectiveness of our pattern selection framework.