Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
A novel wavelet transform based transient current analysis for fault detection and localization
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Review of technology for 157-nm lithography
IBM Journal of Research and Development
Adaptive Debug and Diagnosis Without Fault Dictionaries
Journal of Electronic Testing: Theory and Applications
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Editor's note: Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. This article describes possible solutions to many of these challenges, including statistical timing and delay test, IDDQ test under exponentially increasing leakage, and power or thermal management architectures.--Michael Nicolaidis, iRoC Technologies