IEEE Transactions on Computers
Skew sensitivity minimization of buffered clock tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Convex Optimization
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for sizing sequential circuits for industrial library based designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present an algorithm that performs gate sizing circuit optimization for VLSI designs. Contrary to existing approaches that usually target either clock or data gate sizing as separate optimization steps, our algorithm performs simultaneous optimization of both data and clock gate sizes with common global optimization objective. To do so, we extend traditional gate sizing by Lagrangian Relaxation method with clock-related formulations and use Dynamic Programming to solve those optimally. We demonstrate that on a set of industrial blocks such simultaneous optimization achieves superior results when compared to classical separate optimization flow.