Introduction to algorithms
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimization of power dissipation and skew sensitivity in clock buffer synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Clock tree synthesis for multi-chip modules
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A practical clock router that accounts for the capacitance derived from parallel and cross segments
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous clock and data gate sizing algorithm with common global objective
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Given a topology of clock tree and a library of buffers, we propose an efficient skew sensitivity minimization algorithm using dynamic programming approach. Our algorithm finds the optimum buffer sizes, its insertion levels in the clock tree, and optimum wire widths to minimize the skew sensitivity under manufacturing variations. Careful fine tuning by shifting buffer locations at the last stage preserves the minimum skew sensitivity property and reduces the interconnect length. For a given clock tree of n points and a library of s different buffer sizes, the run time of the presented algorithm is O(log3n•s2).Experimental results show a significant reduction of clock skews ranging from 87 times to 144 times compared to the clock skews before applying the proposed algorithm. We also observe a further reduction of the propagation delay of clock signals as a result of applying the proposed skew sensitivity algorithm.