Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Skew sensitivity minimization of buffered clock tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
Proceedings of the 2003 international symposium on Physical design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
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Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming approaches are often trapped at local minimum and have no guarantee of obtaining global optimal solution. In this paper, we present optimal clock tuning algorithms which effectively apply capacitance-padding to reduce clock skew, power, and delay for general clock topologies. Capacitance-padding can be achieved by wire-spacing, wire-splitting, wire-padding and transistor-padding. We show that under the El-more delay model, capacitance-padding can be formulated as a linear programming problem and solved with great efficiency. Capacitance-padding can also be used as a post processing step for any non-zero-skew clock tree or mesh structure to achieve timing closure. Experiment results on several practical industry examples show that our algorithms are extremely efficient. Problems with over 6000 variables can be optimally tuned within 1 minute on a PC with 500 -MHZ Intel Pentium III processor.