Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
A specified delay accomplishing clock router using multiple layers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock distribution design and verification for PowerPC microprocessors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A practical clock router that accounts for the capacitance derived from parallel and cross segments
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Clocking Optimization and Distribution in Digital Systemswith Scheduled Skews
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Clock Distribution Methodology for PowerPC™Microprocessors
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
A hierarchical decomposition methodology for multistage clock circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
EWA: exact wiring-sizing algorithm
Proceedings of the 1997 international symposium on Physical design
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Optimal reliable crosstalk-driven interconnect optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Statistical clock tree routing for robustness to process variations
Proceedings of the 2006 international symposium on Physical design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variability aware low-power delay optimal buffer insertion for global interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
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