Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Timing Verification and Optimization for the PowerPCTM Processor Family
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Jitter-tolerant clock routing in two-phase synchronous systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient testing of clock regenerator circuits in scan designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
A hierarchical decomposition methodology for multistage clock circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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With the increase of clock speeds, clock skew has become a significant part of the cycle time of high speed microprocessors. While many clocktree routing techniques promise zero or minimal skew, algorithm assumptions or our design methodology constraints often prevent a single approach from being suitable for the entire clock design. In this paper we describe a collection of strategies that are applied at various levels of design to yield clock distribution networks of acceptable skew for the two different clock design styles used by PowerPC processors. We also describe a static timing based approach for analyzing the clock network to detect the various clock violations of interest.