A hierarchical decomposition methodology for multistage clock circuits

Authors:
Gary Ellis;Lawrence T. Pileggi;Rob A. Rutenbar
Affiliations:
IBM Microelectronics, IBM, Austin, TX;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Venue:
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Year:
1997

Citing 6
Cited 1

Clock routing for high-performance ICs

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization

DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings

DAC '93 Proceedings of the 30th international Design Automation Conference
Clock distribution design and verification for PowerPC microprocessors

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Performance of a new annealing schedule

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchical decomposition of the layout divides the problem into a set of local Steiner-wired latch clusters (to minimize and balance local capacitance) fed globally by a balanced binary tree (to maximize performance). Second, we recast the global clock distribution problem as a simultaneous optimization of clock topology, clock segment routing, wiresizing, and buffering. The hierarchical decomposition reduces the problem complexity and allows use of more aggressive optimization techniques. Integration of the geometric and electrical optimizations likewise allows more aggressive performance goals. Experiments with an industrial design comprising over 16,000 latches demonstrate the efficiency of the approach: a complete clock distribution solution met a 200MHz cycle time specification with only 310ps of skew, met strict current density constraints, exhibited good delay matching across uniform wire width and device variations, and was completed in under 10 CPU hours.