Computational geometry: an introduction
Computational geometry: an introduction
Algorithms in C
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
A zero-skew clock routing scheme for VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimization of power dissipation and skew sensitivity in clock buffer synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Clock distribution design and verification for PowerPC microprocessors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Minimizing wirelength in zero and bounded skew clock trees
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock-Skew Constrained Cell Placement
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
System level clock tree synthesis for power optimization
Proceedings of the conference on Design, automation and test in Europe
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
Proceedings of the 2009 international symposium on Physical design
Routing with constraints for post-grid clock distribution in microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock Tree synthesis for TSV-based 3D IC designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
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