System level clock tree synthesis for power optimization

Authors:
Saif Ali Butt;Stefan Schmermbeck;Jurij Rosenthal;Alexander Pratsch;Eike Schmidt
Affiliations:
Chip Vision Design Systems AG, Oldenburg, Germany;Chip Vision Design Systems AG, Oldenburg, Germany;Chip Vision Design Systems AG, Oldenburg, Germany;Chip Vision Design Systems AG, Oldenburg, Germany;Chip Vision Design Systems AG, Oldenburg, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2007

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Abstract

The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall power dissipations are possible by optimizing the clock tree. Although these savings are already relevant at system-level, only little effort has been made to consider the clock tree at higher levels of abstraction. This paper shows how the clock-tree can be integrated into system-level power estimation and optimization. A clock tree routing algorithm is chosen, adapted to the system-level and then integrated into an algorithmic-level power optimization tool. Experimental results demonstrate the importance of the clock tree for system-level power optimization.