Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Energy-performance trade-offs for spatial access methods on memory-resident data
The VLDB Journal — The International Journal on Very Large Data Bases
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
IEEE Transactions on Computers
Compiler-directed high-level energy estimation and optimization
ACM Transactions on Embedded Computing Systems (TECS)
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
System level clock tree synthesis for power optimization
Proceedings of the conference on Design, automation and test in Europe
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.