Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
IEEE Micro
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
System level clock tree synthesis for power optimization
Proceedings of the conference on Design, automation and test in Europe
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A low power Super H embedded processor core, the SH-X2,has been desogned in 90-nm CMOS tehnology. The powerconsumption was reduced by using hierarchical fined grained clock gating to reduce the power consumption of the flip-flops and clock-tree synthesis and layout that support implementation of the clock gating, and several-level power evaluations for FTL refinement. With this clock gating and RTL refinement the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using Renesas low-power process with lowered voltage. Its performance efficiency was 25% better than that of a 130-nm-process SH-X.