A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation

Authors:
Masafumi Onouchi;Tetsuya Yamada;Kimihiro Morikawa;Isamu Mochizuki;Hidetoshi Sekine
Affiliations:
Hitachi Ltd., Higashi-Koigakubo, Kokubunji-shi, Tokyo, Japan;Hitachi Ltd., Higashi-Koigakubo, Kokubunji-shi, Tokyo, Japan;Renesas Technology Corp., Josuihon-cho, Kodaira-shi, Tokyo, Japan;Renesas Technology Corp., Josuihon-cho, Kodaira-shi, Tokyo, Japan;Renesas Technology Corp., Josuihon-cho, Kodaira-shi, Tokyo, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

We have developed a specialized rapid power-estimation methodology for multimedia applications. This methodology has adequate accuracy for the first design of a complicated SoC. For a multimedia application, we developed three new methodologies: an IP-level modeling, a power-level adjustment methodology, and a power accumulation methodology. With these methodologies, the system-level power estimation on a SoC executing a practical application becomes so precise and easy that we can revise the SoC design to reduce its power. According to a comparison of the system-level power estimated with these methodologies to board-measured power, the error between the two powers is less than 5.6%.